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854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 1 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer g eneral d escription the ICS854054 is a 4:1 differential-to-lvds clock multiplexer which can operate up to 2.8ghz and is a member of the hiperclocks? family of high performance clock solutions from ics. the ICS854054 has 4 selectable differential clock inputs. the pclk, npclk input pairs can accept lvpecl, lvds, cml or sstl levels. the fully differential architec- ture and low propagation delay make it ideal for use in clock distribution circuits. the select pins have internal pulldown resistors. the sel1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects pclk0, npclk0). f eatures ? high speed 4:1 differential multiplexer ? one differential lvds output ? four selectable differential clock inputs ? pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, cml, sstl ? maximum output frequency: 2.8ghz ? translates any single ended input signal to lvds levels with resistor bias on npclkx input ? part-to-part skew: 375ps (maximum) ? propagation delay: 700ps (maximum) ? supply voltage range: 3.135v to 3.465v ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs compliant packages b lock d iagram p in a ssignment hiperclocks? ic s pclk0 npclk0 pclk1 npclk1 v dd sel0 sel1 gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd q nq gnd npclk3 pclk3 npclk2 pclk2 ICS854054 16-lead tssop 4.4mm x 5.0mm x 0.92mm package body g package top view pclk0 npclk0 pclk1 npclk1 pclk2 npclk2 pclk3 npclk3 00 11 01 10 sel1 sel0 q nq (default)
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 2 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer t able 1. p in d escriptions t able 2. p in c haracteristics t able 3. c lock i nput f unction t able l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n w o d l l u p r o t s i s e r n w o d l l u p 5 7k r 2 / d d v s r o t s i s e r n w o d l l u p / p u l l u p 0 5k s t u p n is t u p t u o 1 l e s0 l e sqq n 00 0 k l c p0 k l c p n 01 1 k l c p1 k l c p n 10 2 k l c p2 k l c p n 11 3 k l c p3 k l c p n r e b m u ne m a ne p y tn o i t p i r c s e d 10 k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 20 k l c p nt u p n in w o d l l u p / p u l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i v d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 31 k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 41 k l c p nt u p n in w o d l l u p / p u l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i v d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 6 1 , 5v d d r e w o p. s n i p y l p p u s e v i t i s o p 7 , 61 l e s , 0 l e st u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t u p n i t c e l e s k c o l c 3 1 , 8d n gr e w o p. d n u o r g y l p p u s r e w o p 92 k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 0 12 k l c p nt u p n in w o d l l u p / p u l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i v d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 1 13 k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 2 13 k l c p nt u p n in w o d l l u p / p u l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i v d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 5 1 , 4 10 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 3 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 0 9a m t able 4c. lvpecl dc c haracteristics , v dd = 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 3 k l c p : 0 k l c pv d d v = n i v 5 6 4 . 3 =0 5 1a 3 k l c p n : 0 k l c p nv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i 3 k l c p : 0 k l c pv d d v , v 5 6 4 . 3 = n i v 0 =0 1 -a 3 k l c p n : 0 k l c p nv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 02 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 2 . 1v d d v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i x k l c p n r o x k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n d d . v 3 . 0 + a bsolute m aximum r atings supply voltage, v dd 5.5v inputs, v i -0.5v to v dd + 0.5 v outputs, i o continuous current 10ma surge current 15ma package thermal impedance, ja 89c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 4b. lvcmos/lvttl dc c haracteristics , v dd = 3.3v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n iv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n iv d d v , v 5 6 4 . 3 = n i v 0 =0 1 -a
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 4 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer t able 5. ac c haracteristics , v dd = 3.135v to 3.465v, t a = -40c to 85c t able 4d. lvds dc c haracteristics , v dd = 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 0 5 20 5 45 2 5v m v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 5 2 1 . 15 2 . 15 7 3 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 8 . 2z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p 5 2 30 0 7s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b r e t t i j e s a h p e v i t i d d a o t r e f e r n o i t c e s , z h m 2 5 . 5 5 1 ) z h m 0 2 - z h k 2 1 ( 5 9 1 . 0s p t ) p p ( k s3 , 2 e t o n ; w e k s t r a p - o t - t r a p 5 7 3s p t ) i ( k sw e k s t u p n i 0 9s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 50 5 2s p x u m n o i t a l o s i n o i t a l o s i x u m , z h m 2 5 . 5 5 1 v m 0 0 8 = k a e p - o t - k a e p t u p n i 0 5 -b d . e s i w r e h t o d e t o n s s e l n u z h m 5 . 1 o t p u d e r u s a e m s r e t e m a r a p l l a . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w g n i d r o c c a d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 5 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer a dditive p hase j itter additive phase jitter, rms @ 155.52mhz (12khz - 20mhz) = <0.195ps typical 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1m 10m 100m the spectral purity in a band at a specific offset from the funda- mental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fun- damental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in as with most timing specifications, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the de- the 1hz band to the power in the fundamental. when the re- quired offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the funda- mental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. vice meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 6 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer p arameter m easurement i nformation p ropagation d elay d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit p art - to -p art s kew o utput r ise /f all t ime o ffset v oltage nqx qx nqy qy pa rt 1 pa rt 2 t sk(pp) v cmr cross points v pp gnd v dd scope qx nqx lv d s 3.3v5% power supply + - float gnd clock outputs 20% 80% 80% 20% t r t f v od t pd npclk0:3 pclk0:3 nq0 q0 out out lv d s dc input ? ? ? v os / v os v dd npclk0:3 pclk0:3 d ifferential o utput v oltage ? ? ? 100 out out lv d s dc input v od / v od v dd i nput s kew t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) q nq pclk0 npclk0 pclk1 npclk1
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 7 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer a pplication i nformation w iring the d ifferential i nput to a ccept s ingle e nded l evels figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. vdd r2 1k v_ref c1 0.1u r1 1k single ended clock input pclk npclk i nputs : pclk/npclk i nput : for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k resister can be tied from pclk to ground. s elect p ins : all select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. a 1k resister can be used. r ecommendations for u nused i nput p ins
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 8 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show inter- face examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces sug- gested here are examples only. if the driver is from another vendor, use their termination recommendation. please con- sult with the vendor of the driver component to confirm the driver termination requirements. f igure 2a. h i p er c lock s pclk/ n pclk i nput d riven by a cml d river f igure 2b. h i p er c lock s pclk/npclk i nput d riven by an sstl in d river f igure 2c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 2d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v f igure 2e. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 9 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer lvds d river t ermination a general lvds interface is shown in figure 3. in a 100 differential transmission line environment, lvds drivers re- quire a matched load termination of 100 across near the 100 ohm differiential transmission line r1 100 3.3v + - lvds_driv er 3.3v f igure 3. t ypical lvds d river t ermination receiver input. for a multiple lvds outputs buffer, if only par- tial outputs are used, it is recommended to terminate the un- used outputs.
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 10 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS854054. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854054 is the sum of the core power. the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * i dd_max = 3.465v * 90ma = 311.85mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature q ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.312w * 81.8c/w = 110.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 16-l ead tssop, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard t est boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 11 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer r eliability i nformation t ransistor c ount the transistor count for ICS854054 is: 361 t able 7. ja vs . a ir f low t able for 16 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 137.1c/w 118.2c/w 106.8c/w multi-layer pcb, jedec standard test boards 89.0c/w 81.8c/w 78.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 12 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer t able 8. p ackage d imensions p ackage o utline - g s uffix for 16 l ead tssop reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n6 1 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 9 . 40 1 . 5 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
854054ag www.icst.com/products/hiperclocks.html rev. a march 29, 2006 13 integrated circuit systems, inc. ICS854054 4:1 d ifferential - to -lvds c lock m ultiplexer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other ext raordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g a 4 5 0 4 5 8 s c ig a 4 5 0 4 5 8p o s s t d a e l 6 1e b u tc 5 8 o t c 0 4 - t g a 4 5 0 4 5 8 s c ig a 4 5 0 4 5 8p o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l g a 4 5 0 4 5 8 s c id b tp o s s t d a e l 6 1e b u tc 5 8 o t c 0 4 - t f l g a 4 5 0 4 5 8 s c id b tp o s s t d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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